The article is devoted to the development of a tool for automated generation of time constraints in the context of circuit development in the basis of programmable logic integrated circuits (FPGAs). The paper analyzes current solutions in the field of interface tools for generating design constraints. The data structure for the means of generating design constraints and algorithms for reading and writing Synopsys Design Constraints format files have been developed. Based on the developed structures and algorithms, a software module was implemented, which was subsequently implemented into the circuit design flow in the FPGA basis - X-CAD.

Keywords: computer-aided design, field programmable gate array, automation, design constraints, development, design route, interface, algorithm, tool, static timing analysis