The reconfigurable systems-on-a-chip (RSoC) includes hard and soft intellectual property cores (IP-cores). Hard IP-cores are placed on the specified positions on the chip and have a predetermined functionality. Soft IP-cores are developed using the logical blocks (LB) of a field programmable gate array (FPGA) on the RSoC. Both types of IP-cores have different features. Hard IP-cores have configurations that can be programmed. Soft IP-cores use the base RSoC specialized resources. All IP-cores features must be considered at various stages of the design flow of user circuits based on the RSoC. Any modes of the RSoC IP-cores should be extracted from the functional description of the user circuit during logical synthesis. The features of the base chip architecture and specialized routing resources must be considered during placement and routing. In this paper, a software-oriented set-theoretic model of IP-cores is presented. The model makes it possible to represent IP-cores in computer-aided design (CAD) system at different stages of design flow of user circuit based on RSoC and to map architecture-independent IP-cores of a user circuit to IP-cores on the base chip. The model combines formalized representations of the base chip components, architecture-independent and architecture-dependent parameterized IP-cores for the logical synthesis, as well as IP-cores for the layout synthesis. Also, the model has several distinctive features. The first feature is the availability of the relative coordinates of the soft IP-cores elements. These coordinates allow to take into account the RSoC architectural features at the placement stage. The second feature is that an information about specialized routing resources and interconnections of the user and base circuits. This information allows to establish a correspondence between IP-core and RSoC connections regardless of the routing resources type.

Keywords: reconfigurable system-on-a-chip, intellectual property core, field programmable gate array, computer-aided design system, set-theoretic model, formalization

Soft intellectual property cores (IP-cores) based on a field programmable gate array (FPGA) are blocks that do not have a specific placement and prerouted interconnects on the chip. These blocks make it possible to speed up the design process of the digital circuits based on the FPGAs, while the use of the FPGA architecture specialized resources can increase the performance of the developed circuits that include soft IP-cores. These resources should be considered both in the soft IP-cores design and in the development of methods and algorithms for computer-aided design systems to achieve the greatest efficiency. In this paper, two soft IP-cores implementations are developed and a comparative analysis of the obtained blocks’ volumes and the used routing resources is carried out. In the first implementation, both the logical and layout syntheses take into account the basic FPGA structural features and FPGA specialized resources. In the second, only standard library elements and a common routing tree are used. On the results of the analysis, the advantages of the FPGA specialized architecture specialized resources in the soft IP-cores design are shown. Also the paper describes the specifics of these resources introduced by the FPGA developers, and the implementation features of the following soft IP-cores: n-bit adder / subtractor, up counter to n and n-bit shift register.

Keywords: intellectual property core, computer aided design, field programmable gate array, design flow, routing