Investigation of partial backup options in the design of fault-tolerant logic blocks in FPGAs

Abstract

Investigation of partial backup options in the design of fault-tolerant logic blocks in FPGAs

Tel'pukhov D. V., Rukhlov V. S., Ivanova G.A., Ryzhova D.I., Nadolenko V.V., Demeneva A.I.

Incoming article date: 22.01.2018

In this article, we propose methods for designing fault-tolerant structures for Field Programmable Gate Arrays (FPGAs) by forming an internal structure of macro cells (LUTs), with the possibility of correcting single reversible faults in the circuit’s gates. To improve fault tolerance, the failure tolerance of a typical macro cell was assessed, the most vulnerable areas were identified and the most vulnerable parts of the macrocell were protected by means of triple modular redundancy methods. Depending on the expansion of the protected area, various versions of the built-in redundancy were obtained, and various options for minimizing the built-in redundancy were proposed. Experimental work was carried out to form fault-tolerant ISCAS'85 combinational circuit designs in the basis of fault-tolerant FPGAs.

Keywords: combinational circuit, FPGA, field-programmable gate array, LUT, logic synthesis, increase fault tolerant, computer-aided design (CAD), fault injection, single event transient